For DSP device designers, meeting these escalating challenges requires a blending of innovative new chip-level DSP architectures as well as a continuous rapid migration to the most demanding ultra-small semiconductor fabrication processes. In addition to requiring extensive internal DSP design expertise and applications knowledge, the successful implementation of miniaturized DSP designs is now also highly dependent upon effectively leveraging third-party intellectual property (IP) design elements that are pre-optimized for leading-edge fabrication processes.

Here we look at how the internal design team at Dspfactory (Waterloo, Ontario) combined power-conserving circuit designs and worked closely with Nurlogic Design, Inc. (San Diego, CA) to integrate ultra low-power IP elements to build a new family of miniaturized ultra low-power DSP devices. In addition, we review the inter-company coordination (between Dspfactory, Nurlogic, and various IP and foundry suppliers) and communications issues that were key to the project's success.

Design goals and challenges

The design objective was to create a fully software-programmable DSP system on a single chip that can be deployed for a variety of applications ranging from in-the-ear hearing aids to low-power wireless, voice-processing, automotive sensing/control circuits and other miniature system implementations with critical DSP requirements. In order to meet the specific needs of very different applications across this diverse spectrum of end-use scenarios, the miniaturized DSP system also needed to accommodate a wide set of environmental and operating conditions.

For example, in-the-ear hearing aid applications require an ultra-small form factor in order to fit the entire system completely inside the ear canal. Very low power operation is critical for extended battery life. Low-voltage operation is also critical because single battery operation is a requirement for this product. In addition, such devices must also be able to withstand the relatively high ESD (electro-static discharge) levels of approximately 2.5kv that are present during manufacturing and assembly. Alternatively, applications such as wireless or other consumer products can require that the DSP devices deliver reliable performance up to 85 degrees C.

In order to meet the low-power and heat dissipation requirements for in-the-ear hearing aid applications, it was determined that the new DSP devices would need to be designed for ultra-low 0.9 V operation and a .18-micron fab process would be required to achieve the small die size objectives. While it's inherently difficult to maintain timing performance and reliability at .9 V operating levels, it becomes even more challenging when the final devices must be capable of running at up to 85 degrees C.

Structuring the architecture While deep-submicron fabrication technology opens the door for implementing advanced DSP algorithms within very small die sizes, close attention must be given to architectural partitioning as the first step in optimizing the design for minimal space and power, while maximizing flexibility and performance.

Dspfactory's chip-level DSP system design is built around three major components: a weighted overlap-add (WOLA) filterbank co-processor, a 16-bit Harvard DSP core, and a tightly integrated input-output (I/O) processor (see Figure 1). For maximum applications flexibility, both the WOLA and DSP core have access to the I/O processor, as well as direct communication through a shared RAM interface. The I/O processor efficiently handles all of the external dataflow between the DSP system and an off-chip A/D and D/A subsystem. A separate interface to external EEPROM allows for optimizing software programmability for specific configurations.

Incorporating a flexible WOLA into the basic architecture serves the dual purpose of both enhancing configuration flexibility and minimizing power usage. First, power consumption can be minimized because a signal processing architecture optimized for filtering is inherently more power efficient than general-purpose architectures. Secondly, the filterbank's more efficient use of smaller memory structures allows the overall chip size to be reduced.

A critical figure of merit for implementing miniaturized signal processing applications is the amount of energy required for a given level of processing, typically expressed in micro-Joules per Fast Fourier Transform (FFT) operation. Extensive empirical analysis has demonstrated that an efficiently implemented WOLA, such as that used in the Dspfactory design, can yield approximately 4.5 times the performance of dedicated FFT DSPs when power consumption is taken into consideration.

The vast majority of DSP algorithms can be cast into filtering paradigms, which can be efficiently handled by the small-sized hardware WOLA. Various signal processing functions that can be directly processed by the WOLA filterbank within a frequency-domain processing environment include: dynamic range compression, noise reduction, sub-band coding, directional processing, voice activity detection, and echo cancellation. This programmable flexibility allows the DSP system to be readily adapted to a variety of in-the-ear hearing aid implementations and can even enable each system to be tuned to the specific hearing correction requirements of individual users.

The I/O processor contains an interface module that handles all pre- and post-processing for the system, including interpolating and decimation filtering, while minimizing power usage and die real estate requirements. The I/O processor is a block-based direct memory access (DMA) controller that is tightly coupled to the WOLA filterbank. Input samples are stored in a circular FIFO, with WOLA analysis transformations performed on each block of samples. Block floating-point (BFP) computational units are used to increase the dynamic range and reduce quantization error-improving the WOLA's signal-to-noise ratio (SNR), while simultaneously minimizing the computational complexity and power requirements.

Using data stored in the shared RAM, the general purpose DSP core can then efficiently analyze the complex spectrum and apply gains for each frequency band.

By operating on blocks of data in the WOLA and only interrupting the DSP core when necessary, the system design significantly reduces power usage by allowing the DSP core to switch to low-power sleep mode whenever it is not required for spectrum analysis calculations.

Leveraging IP and team

Initially the DSP system-on-a-chip design was proven on 0.35-micron CMOS five-metal layer technology, however development of the ultimate deployable design required moving the design to significantly smaller fabrication technologies.

While .18-micron CMOS four-layer metal technology represented the most viable implementation process, the available standard fabrication alternatives were characterized for 1.8 V and low-power processes were only characterized for 1.5 V operation. In order to meet the ultra low-power objectives, every aspect of the system needed to be efficiently implemented in the .18-micron process and reliably characterized to .9 V power levels.

In order to implement this aggressive new DSP design in the shortest possible timeframe, Dspfactory used a multi-vendor development process, which brought in proven IP solutions targeted to optimize specific aspects of the design.

To complete the multi-disciplinary team and add to internal DSP algorithm expertise, Dspfactory worked with Nurlogic for process-optimized I/O logic and standard cell IP, as well as mixed-signal integration expertise. To provide low-power embedded memory IP solutions, the team also included Virage Logic (Fremont, CA). Key requirements in the selection of IP partners included the existence of .18-micron silicon-proven IP that had been demonstrated to operate at .9 V, which met Dspfactory specified conditions.

Because of the delicate tradeoffs between design components and the severely constrained power and die size requirements, it was critical that all parties work together as a coordinated team to ensure an optimal balance of functionality and on-die resources. For example, including more memory on the device can enhance the overall goals of system programmability and flexibility, however the addition of memory consumes die space that could otherwise be used for additional functionality. Nurlogic's in-depth experience with ultra low-power I/O designs and extensive standard cell libraries was key in meeting the architectural objectives for the I/O processor, in addition to the tight integration of the other on-chip architectural elements.

When working with standard cell libraries and trying to implement at .9 V levels, tradeoffs constantly came into play between cell availability and reliable low-voltage performance. Maintaining sufficient library breadth was important to achieving overall power and die size objectives without compromising functionality. By working closely on design objectives, Nurlogic was able to provide Dspfactory with over 800 cells that were fully characterized for .9 V levels, thereby providing a very viable process for optimal synthesis, density, and performance. Special attention also had to be paid to sequential logic. Due to the nature of the low-voltage designs, sequential logic has a tendency to be more prone to meta-stability problems. By anticipating these sequential logic concerns, some of the standard cells were specifically modified and re-characterized in order to avoid timing and stability issues.

Other challenges included making sure that the core standard cells worked reliably at .9 V while at the same time ensuring that the I/O structures could both operate at .9 V and also withstand ESD up to the specified level of 2.5 kV. By characterizing and implementing the I/O logic at .9 V levels, while leveraging the generic devices that were already available in the foundry's .18-micron process, the team was able to minimize the end product's overall manufacturing costs. To meet Dspfactory's die size objectives, Nurlogic also modified the aspect ratio of the I/O cells in order to support tighter integration.

The need for tight cross-integration between the core logic, I/O, and embedded memory functions required constant open communication throughout the design process, including both regular weekly design review conference calls and day-to-day ad hoc interaction between all team members. With time-to-market issues of great importance in such a project, the close cooperation between IP vendors and the complementary integration of IP is mandated for overall success. One of the more interesting aspects is that virtually the entire communications and coordination process was conducted electronically, with a minimum of face-to-face contact.

One of the key advantages for smoothly handling the integration and implementation process was the ability to quickly adapt the Nurlogic standard cell, I/O, and mixed signal libraries that integrate with Virage Logic's embedded memory structures. The ability to cross-share IP library elements was a vital factor in moving the overall design forward while reducing the challenges of merging different proprietary design elements. This integration of IP elements became especially important in the back-end implementation for resolving issues such as which IP components would use which layers and how the components would physically fit together for optimal results.

Working closely with the selected foundry partner, TSMC, the design team was able to mplement and integrate all aspects of the DSP system architecture and to characterize the entire design for .9 V operation. The constant communication between all members was particularly significant because this project represented one of the early adopters of TSMC's .18-micron CMOS processes.

The proof of concept

At the end of the development process, the approach was proven out with initial silicon that worked the first time, was brought up in less than three hours, successfully tested to prescribed .9 V levels, and was deemed ready to move into full production.

The complete single-chip system was implemented on a .18-micron die measuring less than 10 mm2. Development of the final DSP chip-level system required less than eight months from start to completion and the ultra low-power objectives of .9 V operation were met or exceeded.

These new ultra low-power DSP systems are laying the foundation for the next generation of advanced in-the-ear programmable hearing aids. They also have opened the door for a wide variety of miniature voice-processing and voice-recognition applications in the wireless, automotive, and consumer arenas. By leveraging internal design expertise with third-party IP, these new DSP systems-on-a-chip are providing system-level designers with configurability and programmability, while minimizing overall system size and power usage.

Randy Wayland is with Nurlogic Design, Inc. and Todd Schneider is with Dspfactory, Ltd.